Electronic circuit simulation uses mathematical models to replicate the behavior of an actual electronic device or circuit. Simulation software allows for modeling of circuit operation and is an invaluable analysis tool.
Simulating a circuit's behavior before actually building the circuit can greatly improve design efficiency by making faulty designs known and providing insight into the behavior of the circuit. In particular, for integrated circuits, tooling (e.g., photomasks) is expensive and probing the behavior of internal signals is extremely difficult. Therefore almost all integrated circuit design relies heavily on simulation. A well known analog simulator is SPICE (Simulation Program with Integrated Circuit Emphasis).
The high costs of photolithographic masks and other manufacturing prerequisites make it essential to design a circuit to be as close to perfect as possible before the integrated circuit is first built. Simulating the circuit with SPICE is the industry-standard way to verify circuit operation at the transistor level before committing to manufacturing the integrated circuit.
In electronic design automation, parasitic extraction is the calculation of parasitic effects in both the designed devices and the required wiring interconnects of an electronic circuit such as detailed device parameters, parasitic capacitances, parasitic resistances and parasitic inductances, commonly called parasitic devices, parasitic components, or simply parasitics.
The major purpose of parasitic extraction is to create an accurate analog model of the circuit so that detailed simulations can emulate actual digital and analog circuit responses. Digital circuit responses are often used to populate databases for signal delay and loading calculation such as timing analysis, circuit simulation, and signal integrity analysis.
FastCap and FastHenry, from MIT (Massachusetts Institute of Technology), are two parasitics extractor tools for capacitance, inductance and resistance. Another universal parasitics extractor tool is Star-RCXT from Synopsys (previously from Avanti).
As microprocessors increase in speed, clocks that drive them also need to switch at higher and higher frequencies. The clocks need to be distributed across a chip in a uniform fashion so that the skew between any two points is minimized.
To achieve this goal, wide upper level interconnects are used for clock signal distribution. In wide wires, at advanced processes, inductive effects start to dominate (as opposed to resistive effects for typical narrow wires). Unfortunately, it is much more difficult to model/analyze inductive effects than resistive effects.
Using the existing resistive-capacitive (R-C) analysis methodology, the method only modeled the resistivity of a wire and the electric field around the wire (at the coupling of the wire and surrounding neighboring wires). The analysis resulted in signal propagation delay estimates that were very small and non-physical. With such small delays, the R-C analysis concluded that signals were propagating near or above the speed-of-light. These delay estimates are, of course, incorrect. As a result, buffers designed in a circuit tend to be oversized, wasting area and power. In addition, increased inaccuracy may result for these analysis methods if the clock distribution network is not completely symmetric, which it rarely is.